This invention relates to a bit map image data processing apparatus provided with a plurality of bit map memory planes.
Conventionally, a bit map data processing apparatus using bit map memory planes, such as a bit map display apparatus, is generally constituted as illustrated in FIG. 1. In the bit map data processing apparatus with such a structure, it is assumed that memory plane 11-1 is used for registering of character font data and memory plane 11-2 is used for display. If the character font data is copied from memory plane 11-1 to memory plane 11-2 (between planes), in a first memory cycle a memory read operation is performed in memory plane 11-1 as a source plane, as shown in FIGS. 2A to 2C. Then, in a second memory cycle, a memory write operation is performed in memory plane 11-2 as a destination plane, as shown in FIGS. 2A to 2C. Transfer of image data of one word is carried out in this manner, and the same transfer operation is executed for the subsequent image data.
As should be clear from the above, even if the conventional bit map data processing apparatus has a plurality of memory planes, only one memory plane can function in a single memory cycle, so that data copying between planes undesirably requires two memory cycles for transferring of one word.
Recently, bit map data processing apparatuses should often perform a three-term calculation, namely, a logical operation between memory-resident data P0, image data P1 and image mask pattern P2. This three-term calculation is executed in the conventional bit map image data processing apparatus as shown in FIG. 3. Suppose that memory-resident data P0 is stored in memory plane 11-1, image data P1 in memory plane 11-2, and image mask pattern P2 in memory plane 11-n. In this case, a two-term calculation (an AND operation in an example shown in FIG. 3) between memory plane 11-n as a source plane and memory plane 11-2 as a destination plane is executed first in the operation manner as illustrated in FIGS. 2A to 2C. Then, a two-term operation (an OR operation in the example of FIG. 3) between planes with memory plane 11-2 as the source plane and memory plane 11-1 as the destination plane is similarly executed. In this manner, according to the conventional bit map image data processing apparatus a three-term operation is realized by repeating a two-term operation at least twice. For a three-term operation of one word, therefore, four memory cycles are needed, thus delaying the processing speed.
To overcome this problem, there is a system proposed which sets an image mask pattern in a register or the like as a fixed value so as to eliminate the need to read out the image mask pattern from any memory plane. However, in this system the image mask pattern is restricted. In this respect, there is a strong and growing demand for an image data processing apparatus with a simple structure, which is capable of processing image data with a high speed.